0.6v to 16.5v hot swap controller preliminary technical data adm1170 features allows safe board insertion and removal from a live backplane controls supply voltages from 0.6 v to 16.5v adjustable analog current limit with circuit breaker fast response limits peak fault current automatic retry or latch-off on current fault adjustable supply voltage power-up rate charge pumped gate drive for external n-fet switch true soft start control of initial current profile timer pin allows control over timing functions undervoltage lockout adjustable overvoltage protection 8-pin tsot package applications hot swap board insertion C line cards, raid systems electronic circuit breaker industrial high side switch/circuit breaker applications diagram general description the adm1170 is a hot swap contro ller that allows a board to be safely inserted and removed from a live backplane. the device is capable of hot swapping a supply as low as 0.6v. an internal charge pumped driv er controls the gate of an external high side n-channel fet for a supply voltage ranging from 2.7v to 16.5v. the adm1170 provides the initial timing cycle and allows the gate to be ramped up at an adjustable rate. the adm1170 features a fast current limit loop providing active current limiting together with a circuit breaker timer. the signal at the on pin turns the part on and off and is also used for the reset function. the ss pin allows the user to cont rol the soft start profile of the current ramp at start-up via an external capacitor. a capacitor connected to the timer pin gives the user control over the duty cycle of the pwm retry ratio during current fault. this part is available in two options: the adm1170-1 will automatic retry for over-curre nt fault and the adm1170-2 will latch-off for an over-current fault. the adm1170 is packaged in an 8-lead tsot package. q 1 gate v cc timer on adm1170-1 gnd r sense rs+ v in =1.8v gnd long long short r on1 r on2 c timer c load gnd v out =1.8v ss c ss rs - v in =3.3vaux long rev.prf information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved.
adm1170 preliminary technical data rev. prf | page 2 of 8 adm1170specifications table 1. v cc = 2.7v to 16.5v, t a = -40c to +85c, typical values at t a = 25c unless otherwise noted. parameter min typ max units conditions v cc pin operating voltage range, v cc 2.7 16.5 v supply current, icc 0.5 1.0 ma undervoltage lockout, v uvlo 2.4 2.525 2.65 v v cc rising undervoltage lockout hysteresis, v uvlohys 25 m v on pin on pin input current, i inon -100 0 100 n a on pin threshold, v on 1.26 1.3 1.34 v on rising on pin threshold hysteresis, v onhyst 80 mv rs+/ rs- pin hot swap voltage 0.6 16.5 v sense pin input current, i insense tbd -200 tbd a v sense = v cc , v hotswap = 0.6 v, note 10 20 30 a v sense = v cc , v hotswap > 2.2 v circuit breaker limit voltage, v cb 34 47 60 mv v cb = (v cc C v sense ) ,v hotswap = 0.6 v 44 47 53 mv v cb = (v cc C v sense ) ,v hotswap > 2.2 v over current limit voltage, v oc 40 53 66 mv v hotswap = 0.6 v, note 50 53 59 mv v hotswap > 2.2 v gate pin gate drive voltage, v gate 5 6.5 10 v v gate C v cc , v cc = 2.7v gate drive voltage, v gate 6 8 12 v v gate C v cc , v cc = 5v gate drive voltage, v gate 5 6.5 10 v v gate C v cc , v cc = 16.5v gate pullup current 10 12 14 ua v gate = 0v gate pulldown current 2 ma v gate = 3v, vcc > uvlo gate pulldown current 25 ma v gate = 3v, vcc < uvlo soft start (ss) pin soft start pullup current 10 a current setting gain 20 v/v vss/vsense soft start completion voltage 1 v pull-down current 100 a fault timer pin timer pin pull-up current, i timerup -4 -5 -6 a initial cycle, v timer = 1v -48 -60 -72 a during current fault, v timer = 1v timer pin pull-down current, i timerdn 2 2.5 a after current fault, v timer = 1v 100 a normal operation, v timer = 1v timer pin threshold high, v timerh 1.235 1.3 1.365 v timer rising timer pin threshold low, v timerl 0.18 0.2 0.22 v timer falling
preliminary technical data adm1170 rev. prf | page 3 of 8 absolute maximum ratings table 2. adm1170 absolute maximum ratings parameter rating v cc pin 20v rs+, rs- pins -0.3v to 20v v sense = (rs+ - rs-) 1v timer pin -0.3v to 20v ss pin -0.3v to 20v on pin -0.3v to 20v gate pin v cc + 11v power dissipation tbd storage temperature C65c to +125c operating temperature range C40c to +85c lead temperature range (10 sec) 300c junction temperature 150c
adm1170 preliminary technical data rev. prf | page 4 of 8 hot circuit insertion when circuit boards are inserted into live backplanes, the supply bypass capacitors can dr aw large transient currents from the backplane power bus as they charge. such transient currents can cause permanent damage to connector pins, glitches on the system supply or reset other boards in the system. the adm1170 is designed to tu rn a printed circuit boards supply voltage on and off in a controlled manner, allowing the circuit board to be safely in serted into or removed from a live backplane. the adm1170 ca n reside either on the backplane or on the daughter board for hot circuit insertion applications. overview the adm1170 is designed to operate over a range of supplies from 2.7v to 16.5v and is capa ble of hot swapping as low as 0.6v. upon insertion, an un dervoltage lockout circuit determines if sufficient supply voltage is present. when the on pin goes high an initial timing cycle assures that the board is fully seated in the backplane before the fet is turned on. a single timer capacitor sets th e periods for all of the timer functions. after the initial timing cycle the adm1170 can either start up in current limi t or with a lower load current. once the external fet is fully enhanced and the supply has ramped up, the adm1170 monitors the load current through an external sense resistor. overcurrent faults are actively limited to 47mv/r sense for a specified circuit breaker timer limit. the adm1170-1 will automa tically retry after a current limit fault while the adm1170- 2 latches off. the adm1170-1 timer function limits the retry duty cycle to 3.8% for fet cooling. undervoltage lockout an internal undervoltage lock out (uvlo) circuit resets the adm1170 if the v cc supply is too low for normal operation. the uvlo has a low-to-high threshold of 2.5255v, a 25mv hysteresis. above 2.525v supply voltage, the adm1170 will start if the on pin conditions are met. on function the on pin is the input to a comparator which has a low-to- high threshold of 1.3v, an 80mv hysteresis and a high-to- low glitch filter of 30 s and a low-to-high glitch filter of 3us. a low input on the on pin rese ts the adm1170 timer status and turns off the external fet by pulling the gate pin to ground. a low-to-high transition on the on pin starts an initial cycle followed by a start-up cycle. a 10k pull-up resistor connecting the on pin to the supply is recommended. the 10k resistor shunts any potential stat ic charge on the backplane and reduces the overvoltage stress at the on pin during live insertion. alternatively, an external resist or divider at the on pin can be used to program an undervoltage lockout value higher than the internal uvlo circuit. an rc filter can be added at the on pin to increase the delay time at card insertion if the internal glitch filter delay is insufficient. gate function during hot insertion of the pcb, an abrupt application of supply voltage charges the external fet drain/gate capacitance. this can cause an unwanted gate voltage spike. an internal circuit holds gate low before th e internal circuitry wakes up. this reduces the fet current surg es substantially at insertion. the gate pin is held low in reset mode and during the initial timing cycle. in the start-up cycle the gate pin is pulled up by a 12 a current source. during an over-current fault condition, the error amplifier servos the gate pin to maintain a constant current to the load until the circuit breaker trips. when the circuit breaker trips, the ga te pin shuts down abruptly. current limit circuit breaker function the adm1170 features a current limiting circuit breaker. when there is a sudden load current surge, such as a low impedance fault, the bus supply voltage can drop significantly to a point where the power to an adjacent card is affected, causing system ma lfunctions. the adm1170 high bandwidth current control loop limits current by reducing the external fet gate pin voltage. this minimizes the bus supply volt age drop and permits power budgeting and fault isolation without affecting neighbouring cards. calculating current limit the nominal fault current limit is determined by a sense resistor connected between v cc and the sense pin as given by the equation below: i limit(nom) = v cb(nom) / r sense (1) the minimum load current is given by equation 2: i limit(min) = v cb(min) / r sense(max) (2) the maximum load current is given by equation 3: i limit(max) = v cb(max) / r sense(min) (3) note: the power rating of the sens e resistor should be rated at the fault current level. for proper operation, the minimum current limit must exceed the circuit maximum operating load current with margin. the sense resistor power rating must exceed v cb(max ) 2 /r sense(min).
preliminary technical data adm1170 rev. prf | page 5 of 8 timer function the timer pin handles several key functions with an external capacitor, c timer . there are two comparator thresholds: comp1 (0.2v) and comp2 (1.3v) . the four timing current sources are: ? 5 a pull-up ? 60a pull-up ? 2a pull-down ? 100a pull-down the 100a is a non-id eal current source approximating a 7k resistor below 0.4v. initial timing cycle when the card is being inserted into the bus connector, the long pins mate first which brings up the supply vin at time point 1 of figure 3. the adm1170 is in reset mode as the on pin is low. gate is pulled low and the timer pin is pulled low with a 100a source. at time point 2, the short pin makes contact and on is pulled high. at this instant, a start-up check requires that the supply voltage be above uvlo, the on pin beabove1.3vand the timer pin voltage be less than 0.2v. when these three conditions ar e fulfilled, the initial cycle begins and the timer pin is pulled high with 5a. at time point 3, the timer reaches the comp2 threshold and the first portion of the initial cycle ends . the 100a current source then pulls down the timer pin until it reaches 0.2v at time point 4. the initial cycle delay (time point 2 to time point 4) is related to c timer by equation: t initial ~= 272.9 x c timer ms/uf (4) when the initial cycle terminates, a start-up cycle is activated and the gate pin ramps high. the timer pin continues to be pulled down towards ground. soft start (ss pin) the ss pin is used to determine the inrush current profile. a capacitor should be attached to this pin. whenever the fet is requested to turn on, the ss pin is held at ground until the sense voltage reaches a few mv. a current source is then turned on, which linearly ramps the capacitor up to 1v. the reference voltage for the gate linear control amplifier is derived from the soft start voltag e, such that the inrush linear current limit is defined as: i limit = v ss / (20 x r sense ) v in v on v gate v ou t reset m o d e v timer initial cycle start-up cycle norm al cycle figure 1: normal start-up v in v on v gate v out reset mode v timer initial cycle start-up cycle normal cycle i rsense 5a 100a 60a 2a 100a v th figure 2: current limiting at start-up
adm1170 preliminary technical data rev. prf | page 6 of 8 kelvin sense resistor connection when using a low-value sense resistor for high current measurement the problem of para sitic series resistance can arise. the lead resistance can be a substantial fraction of the rated resistance making the total resistance a function of lead length. this problem can be avoided by using a kelvin sense connection. this type of connection separates the current path through the resistor and the vo ltage drop across the resistor. figure 18 below shows the corre ct way to connect the sense resistor between the rs+ and rs- pins of the adm1170. sense resistor kelvin sense traces current flow to -48v backplane current flow from load sense v ee adm1073 current flow to load current flow from source rs+ rs-
preliminary technical data adm1170 rev. prf | page 7 of 8 pin configurations 1 2 3 v cc rs- gnd adm1170-2art top view (not to scale) rs+ timer 8 7 gate on-clr 4 5 6 ss 1 2 3 v cc rs- gnd adm1170-1art top view (not to scale) rs+ timer 8 7 gate on 4 5 6 ss pin functional descriptions pin no. name description 1 timer timer input pin. an external capacitor c timer sets a 272.9ms/ f initial timing delay and a 21.7ms/ f circuit breaker delay. the gate pin tu rns off whenever the timer pin is pulled beyond the upper threshold, such as for o vervoltage detection with an external zener. 2 gnd chip ground pin 3 ss soft start pin. an external capacitor between the ss pin and gnd sets the ramp rate of the load current profile at initial connection. 4 on (on-clr) input pin. the on pin comparator has a lo w-to-high threshold of 1.3v with 80mv hysteresis and a glitch filter. when the on pin is low, the adm1170 is reset. when the on pin goes high, the gate turns on after the initial timing cycle. on the adm1170-2, a rising edge on this pin has the added functi on of clearing a fault and restarting the device 5 gate gate output pin. this pin is the high side ga te drive of an external n-channel fet. an internal charge pump provides a 12a pull- up current with zener clamps to rs+ and ground. in overload, the error amplifier (ea) controls the external fet to maintain a constant load current. 6,7 rs+, rs- current limit sense input pins. a sense resist or between the rs+ and rs- pins sets the analog current limit. in overload, the ea cont rols the external fet ga te to maintain the sense voltage at 47mv. when the ea is main taining current limit, the timer circuit breaker mode is activated. the current limit loop/circuit breaker mode can be disabled by connecting the rs+ pin and rs- pin together. 8 v cc positive supply input pin. the operating supply voltage range is between 2.7v to 16.5v. an undervoltage lockout (uvlo) circuit with a glitch filter resets the adm1170 when a low supply voltage is detected.
outline dimensions figure 3. 8-lead tsot package (uj-8)?dimensions shown in millimeters esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. table 3. ordering guide part number version temperature packag e package description package outline adm1170-1auj automatic retry version ?40c to +85c tsot uj-8 ADM1170-2AUJ latched off versio n ?40c to +85c tsot uj-8 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the proper ty of their respective companies. printed in the u.s.a.
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